翰顺联电子科技(南京)有限公司
江苏省南京市高淳区
SD/SSD IC设计工程师
Responsibilities:
1. RTL/Digital circuit design, synthesis, and simulation/verification.
2. FPGA synthesis, verification.
3. Chip integration, algorithm implementation, and interface design.
4. Generate test pattern.
Qualifications:
1. Familiar with Verilog coding、Design Compiler & STA timing closure.
2. Familiar with digital serial link IP design、Platform integration & tape out flow.
3. Experience in FPGA verification、SATA/PCIe I/O & OEM project design is a plus.
Education:
硕士
Tools:
RTL, Verilog
kecheng.liu@mytekcentral.com.cn